It looks like there may be two more problems in the USB 2.0 core
controller.

1) An IN pkt issued to an empty BULK endpoint causes bad things to
happen. The DMA tries to fetch data, but since the counter is at 0,
it wraps to a big number and the DMA tries to send LOTS of data back
to the host.

2) If the Wishbone interface is writing to the SRAM buffer while an IN
packet is being processed, the data being sent to the host can be
corrupted. The data pipeling in the usbf_idma.v is note quite correct.

Is anybody doing any maintenance on the core at this point?

John Providenza