Apologies for a long email - I've tried to give as much information as I can to avoid people keep having to ask for it. Apologies if it's not all relevant. I am trying to build a USB 1.1 device with 2 endpoints - 1 interrupt IN and 1 interrupt OUT. To start with, I am trying a simple loopback device - any data sent to the device on the OUT endpoint should be returned on the IN endpoint. However, I can't even get the device to be recognised, let alone do anything useful. I think I have connected the core correctly, and changed usb1_rom1.v, but have not had any success. I've attached these files: - testusb.vhd - VHDL file instantiating the core - testusb.scd - constraints file - usb1_rom1.v - modified ROM All other files are as they come from the opencores projects (usb1_funct, usb_phy, generic_fifos, common/generic_memories) I am using an Altera Cyclone EP1C12Q240C8 FPGA on the UP3 development board, which incorporates a USB1T11A PHY chip and relevant clocks. Software is Synplicity Synplify Pro 8.2.1 and Altera Quartus II 5.1. When I compile the code in Synplify, I get 276 warnings, mostly one of: - Case statement has both a full_case directive and a default clause. The full_case directive is ignored. - Unrecognized synthesis directive enum - Unrecognized synthesis directive state - Various warnings about unconnected signals and things being optimised out I don't think these are a problem. Several which may be a problem (I'm not sure) are like: - ...\usb1_funct\rtl\verilog\usb1_pe.v":337:4:337:17|Case tag overlaps with a previous tag (case branches 1 and 2) - ...\usb1_funct\rtl\verilog\usb1_pe.v":339:4:339:17|Case tag overlaps with a previous tag (case branches 1 and 3) - ...\usb1_funct\rtl\verilog\usb1_pe.v":340:4:340:17|Case tag overlaps with a previous tag (case branches 1 and 4) - ...\usb1_funct\rtl\verilog\usb1_pe.v":341:4:341:17|Case tag overlaps with a previous tag (case branches 1 and 5) There are a lot of these. Quartus gives the following warnings: - Port "data_b" on the entity instantiation of "I_1_Z" is connected to a signal of width 1. The formal width of the signal in the module is 8. Extra bits will be driven by GND. (I don't know what's causing this) - Port "data_b" on the entity instantiation of "I_1_Z" is connected to a signal of width 1. The formal width of the signal in the module is 8. Extra bits will be driven by GND. (I don't know what's causing this) - Port "data_b" on the entity instantiation of "I_1_Z" is connected to a signal of width 1. The formal width of the signal in the module is 8. Extra bits will be driven by GND. (I don't know what's causing this) - Port "data_b" on the entity instantiation of "I_1_Z" is connected to a signal of width 1. The formal width of the signal in the module is 8. Extra bits will be driven by GND. (I don't know what's causing this) - Output pins are stuck at VCC or GND (This I know and is deliberate) - Pin "n_clk_cpu_stop" stuck at VCC (This I know and is deliberate) - Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results (This I know and is deliberate) - Can't achieve timing requirement Clock Setup: 'clk_usb' along 210 path(s). See Report window for details. ( I don't know what to do about this) - Can't achieve timing requirement Clock Setup: 'clk_cpu' along 107 path(s). See Report window for details. ( I don't know what to do about this) When I program this onto the FPGA, and connect a USB cable, windows detects a "USB Device", but can not install a driver for it (understandable, since I haven't yet created one). Using the "inf-wizard" from libusb-win32 (http://libusb-win32.sourceforge.net/) reveals a device with vendor ID and product ID both 0x0000. This may be good, except that this much happens even if the FPGA has not been programmed! The vendor ID should be 0x1234, and the device ID 0x5678. I have tried altering several things, but have failed to get any better than this. Any help/advice to get a working device would be very much appreciated. If I've missed any information you need in order to help, just ask. Many thanks, Mark. -------------- next part -------------- library ieee; use ieee.std_logic_1164.all; entity testusb is port (clk_usb, clk_cpu, n_rst, phy_rx_dp, phy_rx_dn, phy_rx_d: in std_logic; n_clk_cpu_stop, phy_tx_dp, phy_tx_dn, phy_tx_oe: out std_logic); -- dout: out std_logic_vector(3 downto 0)); end entity testusb; --INPUTS REQUIRED:- --- clk_usb (48MHz) --- clk_cpu (100MHz) --- n_rst --- phy_rx_dp --- phy_rx_dn --- phy_rx_d --OUTPUTS REQUIRED:- --- phy_tx_dp --- phy_tx_dn --- phy_tx_oe --SIGNALS REQUIRED:- --- usb_rst --- ep_busy --- ep_sel --- infifo_din --- infifo_we --- infifo_dout --- infifo_re --- infifo_full --- infifo_empty --- outfifo_din --- outfifo_we --- outfifo_dout --- outfifo_re --- outfifo_full --- outfifo_empty architecture rtl of testusb is type states is (Idle, Transfer1, Transfer2, Transfer3); signal pstate, nstate: states; signal usb_rst, ep_busy: std_logic; signal infifo_we, infifo_re, infifo_full, infifo_empty: std_logic; signal outfifo_we, outfifo_re, outfifo_full, outfifo_empty: std_logic; signal ep_sel: std_logic_vector(3 downto 0); signal infifo_din, infifo_dout, outfifo_din, outfifo_dout: std_logic_vector(7 downto 0); -- signal n_cpu_clk: std_logic; -- signal ffclk: std_logic; -- Endpoint Configuration Constants constant epIN: std_logic_vector(13 downto 0) := "00001000000000"; constant epOUT: std_logic_vector(13 downto 0) := "00010000000000"; constant CTRL: std_logic_vector(13 downto 0) := "10100000000000"; constant ISO: std_logic_vector(13 downto 0) := "01000000000000"; constant BULK: std_logic_vector(13 downto 0) := "10000000000000"; constant INT: std_logic_vector(13 downto 0) := "00000000000000"; component usb1_core is port (clk_i, rst_i: in std_logic; -- USB PHY Interface tx_dp, tx_dn, tx_oe: out std_logic; rx_d, rx_dp, rx_dn: in std_logic; -- USB Misc phy_tx_mode: in std_logic; usb_rst: out std_logic; -- Interrupts dropped_frame, misaligned_frame: out std_logic; crc16_err: out std_logic; -- Vendor Features v_set_int, v_set_feature: out std_logic; wValue: out std_logic_vector(15 downto 0); wIndex: out std_logic_vector(15 downto 0); vendor_data: in std_logic_vector(15 downto 0); -- USB Status usb_busy: out std_logic; ep_sel: out std_logic_vector(3 downto 0); -- Endpoint Interface ep1_cfg: in std_logic_vector(13 downto 0); ep1_din: in std_logic_vector(7 downto 0); ep1_we: out std_logic; ep1_full: in std_logic; ep1_dout: out std_logic_vector(7 downto 0); ep1_re: out std_logic; ep1_empty: in std_logic; ep1_bf_en: in std_logic; ep1_bf_size: in std_logic_vector(6 downto 0); ep2_cfg: in std_logic_vector(13 downto 0); ep2_din: in std_logic_vector(7 downto 0); ep2_we: out std_logic; ep2_full: in std_logic; ep2_dout: out std_logic_vector(7 downto 0); ep2_re: out std_logic; ep2_empty: in std_logic; ep2_bf_en: in std_logic; ep2_bf_size: in std_logic_vector(6 downto 0); ep3_cfg: in std_logic_vector(13 downto 0); ep3_din: in std_logic_vector(7 downto 0); ep3_we: out std_logic; ep3_full: in std_logic; ep3_dout: out std_logic_vector(7 downto 0); ep3_re: out std_logic; ep3_empty: in std_logic; ep3_bf_en: in std_logic; ep3_bf_size: in std_logic_vector(6 downto 0); ep4_cfg: in std_logic_vector(13 downto 0); ep4_din: in std_logic_vector(7 downto 0); ep4_we: out std_logic; ep4_full: in std_logic; ep4_dout: out std_logic_vector(7 downto 0); ep4_re: out std_logic; ep4_empty: in std_logic; ep4_bf_en: in std_logic; ep4_bf_size: in std_logic_vector(6 downto 0); ep5_cfg: in std_logic_vector(13 downto 0); ep5_din: in std_logic_vector(7 downto 0); ep5_we: out std_logic; ep5_full: in std_logic; ep5_dout: out std_logic_vector(7 downto 0); ep5_re: out std_logic; ep5_empty: in std_logic; ep5_bf_en: in std_logic; ep5_bf_size: in std_logic_vector(6 downto 0); ep6_cfg: in std_logic_vector(13 downto 0); ep6_din: in std_logic_vector(7 downto 0); ep6_we: out std_logic; ep6_full: in std_logic; ep6_dout: out std_logic_vector(7 downto 0); ep6_re: out std_logic; ep6_empty: in std_logic; ep6_bf_en: in std_logic; ep6_bf_size: in std_logic_vector(6 downto 0); ep7_cfg: in std_logic_vector(13 downto 0); ep7_din: in std_logic_vector(7 downto 0); ep7_we: out std_logic; ep7_full: in std_logic; ep7_dout: out std_logic_vector(7 downto 0); ep7_re: out std_logic; ep7_empty: in std_logic; ep7_bf_en: in std_logic; ep7_bf_size: in std_logic_vector(6 downto 0) ); end component usb1_core ; component generic_fifo_dc is generic (dw: integer := 8; aw: integer := 8; n: integer := 32); port (rd_clk: in std_logic; wr_clk: in std_logic; rst: in std_logic; clr: in std_logic; din: in std_logic_vector(dw-1 downto 0); we: in std_logic; dout:out std_logic_vector(dw-1 downto 0); re: in std_logic; full:out std_logic; empty:out std_logic; full_n:out std_logic; empty_n:out std_logic; level: out std_logic_vector(1 downto 0) ); end component generic_fifo_dc; begin usbcore: usb1_core port map ( clk_i=>clk_usb, rst_i=>n_rst, -- USB PHY Interface tx_dp=>phy_tx_dp, tx_dn=>phy_tx_dn, tx_oe=>phy_tx_oe, rx_d=>phy_rx_d, rx_dp=>phy_rx_dp, rx_dn=>phy_rx_dn, -- USB Misc phy_tx_mode=>'1', usb_rst=>usb_rst, -- Interrupts dropped_frame=>open, misaligned_frame=>open, crc16_err=>open, -- Vendor Features v_set_int=>open, v_set_feature=>open, wValue=>open, wIndex=>open, vendor_data=>(others=>'0'), -- USB Status usb_busy=>ep_busy, ep_sel=>ep_sel, -- Endpoint Interface ep1_cfg=>INT or epIN or "00000001000000", --Interrupt In endpoint, max packet size 64 (0x40) ep1_dout=>open, ep1_we=>open, ep1_full=>'0', ep1_din=>infifo_dout, ep1_re=>infifo_re, ep1_empty=>infifo_empty, ep1_bf_en=>'0', ep1_bf_size=>(others=>'0'), -- ep2_cfg=>INT or epOUT or "00000001000000", --Interrupt Out endpoint, max packet size 64 (0x40) ep2_dout=>outfifo_din, ep2_we=>outfifo_we, ep2_full=>outfifo_full, ep2_din=>(others=>'0'), ep2_re=>open, ep2_empty=>'0', ep2_bf_en=>'0', ep2_bf_size=>(others=>'0'), -- ep3_cfg=>(others=>'0'), ep3_din=>(others=>'0'), ep3_we=>open, ep3_full=>'0', ep3_dout=>open, ep3_re=>open, ep3_empty=>'0', ep3_bf_en=>'0', ep3_bf_size=>(others=>'0'), -- ep4_cfg=>(others=>'0'), ep4_din=>(others=>'0'), ep4_we=>open, ep4_full=>'0', ep4_dout=>open, ep4_re=>open, ep4_empty=>'0', ep4_bf_en=>'0', ep4_bf_size=>(others=>'0'), -- ep5_cfg=>(others=>'0'), ep5_din=>(others=>'0'), ep5_we=>open, ep5_full=>'0', ep5_dout=>open, ep5_re=>open, ep5_empty=>'0', ep5_bf_en=>'0', ep5_bf_size=>(others=>'0'), -- ep6_cfg=>(others=>'0'), ep6_din=>(others=>'0'), ep6_we=>open, ep6_full=>'0', ep6_dout=>open, ep6_re=>open, ep6_empty=>'0', ep6_bf_en=>'0', ep6_bf_size=>(others=>'0'), -- ep7_cfg=>(others=>'0'), ep7_din=>(others=>'0'), ep7_we=>open, ep7_full=>'0', ep7_dout=>open, ep7_re=>open, ep7_empty=>'0', ep7_bf_en=>'0', ep7_bf_size=>(others=>'0') ); infifo: generic_fifo_dc generic map (dw=>8, aw=>6, n=>0) port map (rd_clk=>clk_usb, wr_clk=>(not clk_cpu), rst=>'1', clr=>not(n_rst), din=>infifo_din, we=>infifo_we, dout=>infifo_dout, re=>infifo_re, full=>infifo_full, empty=>infifo_empty, full_n=>open, empty_n=>open, level=>open ); outfifo: generic_fifo_dc generic map (dw=>8, aw=>6, n=>0) port map (rd_clk=>(not clk_cpu), wr_clk=>clk_usb, rst=>'1', clr=>not(n_rst), din=>outfifo_din, we=>outfifo_we, dout=>outfifo_dout, re=>outfifo_re, full=>outfifo_full, empty=>outfifo_empty, full_n=>open, empty_n=>open, level=>open ); -- flipflop: entity WORK.flipflop port map(clk=>ffclk, din=>outfifo_dout(3 downto 0), dout=>dout); infifo_din outfifo_re outfifo_re outfifo_re outfifo_re http://www.opencores.org/forums.cgi/usb/attachments/20060103/c9912c29/testusb-0001.sdc -------------- next part -------------- ///////////////////////////////////////////////////////////////////// //// //// //// Descriptor ROM //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi at asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb1_funct///// //// //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000-2002 Rudolf Usselmann //// //// www.asics.ws //// //// rudi at asics.ws //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// //// POSSIBILITY OF SUCH DAMAGE. //// //// //// ///////////////////////////////////////////////////////////////////// // CVS Log // // $Id: usb1_rom1.v,v 1.1.1.1 2002/09/19 12:07:29 rudi Exp $ // // $Date: 2002/09/19 12:07:29 $ // $Revision: 1.1.1.1 $ // $Author: rudi $ // $Locker: $ // $State: Exp $ // // Change History: // $Log: usb1_rom1.v,v $ // Revision 1.1.1.1 2002/09/19 12:07:29 rudi // Initial Checkin // // // // // // `include "usb1_defines.v" module usb1_rom1(clk, adr, dout); input clk; input [6:0] adr; output [7:0] dout; reg [7:0] dout; always @(posedge clk) case(adr) // synopsys full_case parallel_case // ==================================== // ===== DEVICE Descriptor ===== // ==================================== 7'h00: dout