Hi

I write a PHY for full speed USB and intend to use usb_2 as verifcation
part.
In the test bench I inserted jitter, which is supposed to be 0.25% on
12Mhz.

Does someone know if a PHY should output valid data in jittery
environement or just report CRC error.

I use the following code in test bench in generating the TX 48MHz clock:

integer tx_jit;
integer tx_jit_d;//delta
reg [2:0] tx_jit_q;//counter
wire [2:0] tx_jit_i;//counter

assign tx_jit_i=
(tx_jit_q !== 3'd4) ? (tx_jit_q + 3'd1) : 3'd0;

always @ (posedge usb_rx_clk) begin
rand_val tx_jit_q end //of always

`ifdef TX_JIT_ON
always @ (tx_jit_q or rand_val) begin
if(tx_jit_q === 3'd4) begin
if(rand_val else begin
if(rand_val > 4'd5 && rand_val else tx_jit_d=0;
end
end
else tx_jit_d=0;
end
`else
initial tx_jit_d=0;
`endif

initial begin
rand_val=0;
tx_jit_q=3'd0;
tx_jit_d=0;
my_vcc=1'b1;
usb_div_clk_reg=1'b0;
forever begin
tx_jit=42 + tx_jit_d;
#tx_jit
//$display("tx_jit %d ", tx_jit);
//#42
usb_div_clk_reg=1'b1;
#42
usb_div_clk_reg=1'b0;
end
end
assign usb_div_clk=usb_div_clk_reg;