Hello I 'm creating a verification environment (in "c") for USB Design (in "verilog")which will be reusable and automated. Can u suggest me some link or any specific material for this, i had already gone through the standard USB pdf. with regards Raj -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/usb/attachments/20060202/9972b643/attachment.htm