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usb 1.1 core Enumeration Problem
by Unknown on Apr 10, 2007 |
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hello,
im a student at the Fachhochschule Offenburg in Germay and im currently working on my diploma work. we have downloaded the free usb 1.1 IP core (from rudolf usselmann) for our project. im using the CYCLONE II FPGA EP2C8T144 from ALTERA. now im trying to implement the usb module to communicate with the host PC. The current problem is that the Enumeration Process does not work properly. After my Device has recieved the SETUP Paket, it tries to send the first Device Descriptor located in the ROM, but he sends the first byte twice, which results to an incorrect Device Descriptor. So the Host PC terminates the connection and the Enumeration Process fails. It is interesting to see that the Host PC accepts the paket with an ACK, so there cant be any data corruption on the Physical Layer. I have analyzed the communication with an USB protocol analyzer. the ROM content in HEX for the Device Descriptor is: 12, 01, 10, 01, 00, 00, 00, 40, 34, 12, 78, 56, 10, 00, 01, 02, 00, 01 the data content of the paket which the Device wants to send is: 12, 12, 01, 10, 01, 00, 00, 00, 40, 34, 12, 78, 56, 10, 00, 01, 02, 00 here the byte 12h has been send two times. i think that this is the reason for the enumeration failure. Maybe it could be an incorrect initialisation (reset) or an incorrect ROM or FIFO data transmission ? I would be glad someone can help me trying to find out what the problem is and what to do. ------------ my tools: RTL Compilation and Synthesis: Mentor Precision Synthesis; Full Synthesis: Altera Quartus II 6.0 implemented RAMS for FIFO and ROM: altera synchronous ram (altsyncram) |
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usb 1.1 core Enumeration Problem
by Unknown on Apr 27, 2007 |
Not available! | ||
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Hi
It might be due to your ROM connection. Did you simulate yor design
.
Since you captured the data with a protocol analyzer, you may want to
"play it back" in simulation. If you are lucky and it fails you'll be
able to debug the design as a white box (able to see on wave any
signal) instaed of black box (in the lab).
I have once created a verilog environement, which does the entire
process of enumeration in a same a XP master does it. It would be
intersting to try it again.
----- Original Message -----
From: noisehammer at onlinehome.denoisehammer at o...>
To:
Date: Tue Apr 10 19:46:21 CEST 2007
Subject: [usb] usb 1.1 core Enumeration Problem
hello,
im a student at the Fachhochschule Offenburg in Germay and im currently working on my diploma work. we have downloaded the free usb 1.1 IP core (from rudolf usselmann) for our project. im using the CYCLONE II FPGA EP2C8T144 from ALTERA. now im trying to implement the usb module to communicate with the host PC. The current problem is that the Enumeration Process does not work properly. After my Device has recieved the SETUP Paket, it tries to send the first Device Descriptor located in the ROM, but he sends the first byte twice, which results to an incorrect Device Descriptor. So the Host PC terminates the connection and the Enumeration Process fails. It is interesting to see that the Host PC accepts the paket with an ACK, so there cant be any data corruption on the Physical Layer. I have analyzed the communication with an USB protocol analyzer. the ROM content in HEX for the Device Descriptor is: 12, 01, 10, 01, 00, 00, 00, 40, 34, 12, 78, 56, 10, 00, 01, 02, 00, 01 the data content of the paket which the Device wants to send is: 12, 12, 01, 10, 01, 00, 00, 00, 40, 34, 12, 78, 56, 10, 00, 01, 02, 00 here the byte 12h has been send two times. i think that this is the reason for the enumeration failure. Maybe it could be an incorrect initialisation (reset) or an incorrect ROM or FIFO data transmission ? I would be glad someone can help me trying to find out what the problem is and what to do. ------------ my tools: RTL Compilation and Synthesis: Mentor Precision Synthesis; Full Synthesis: Altera Quartus II 6.0 implemented RAMS for FIFO and ROM: altera synchronous ram (altsyncram) |
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