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Testbench code for usb2.0 core (wishbone compilant)
by Unknown on Sep 10, 2008
Not available!
Hi all,
I am working on the verilog testbench for the usb2.0 core
(wish bone compliant). I need some clarifications about the testbench.

1) Do we need precise timing of the utmi signals as per the utmi xcvr
specs. for watching the usb2.0 core to work
2) What is the procedure to setup the configuration of the usb2.0 at
the first step. I am aware of the protocol of the usb2.0. How to
convert them to utmi, wbc signals.
3) Has anyone already written the testbench for the usb2.0 core. Can
anyone guide me in testing the core. I am working on a project that
uses the usb2.0 core(software). I need to see it working working
before I can interface it with other modules in my project.

Thank you for your time. Suggestions are welcomed.

Regards,

Manjunath
Testbench code for usb2.0 core (wishbone compilant)
by Unknown on Sep 10, 2008
Not available!
Hi Manjunath, Im also planning to test my usb2.0 core in future.however im still at the development stages of the core.im not developing it for wishbone compliant as you have mentioned in your query.i would be intrested in knowledge sharing about the core itself as im relatively new but i have to execute a project for my client which deals with USB2.0 based data transfer. please kindly acknowledge my request. Thanks in advance. On Wed, Sep 10, 2008 at 5:09 AM, manjunath_sirigiri at hotmail.com> wrote:
Hi all, I am working on the verilog testbench for the usb2.0 core (wish bone compliant). I need some clarifications about the testbench. 1) Do we need precise timing of the utmi signals as per the utmi xcvr specs. for watching the usb2.0 core to work 2) What is the procedure to setup the configuration of the usb2.0 at the first step. I am aware of the protocol of the usb2.0. How to convert them to utmi, wbc signals. 3) Has anyone already written the testbench for the usb2.0 core. Can anyone guide me in testing the core. I am working on a project that uses the usb2.0 core(software). I need to see it working working before I can interface it with other modules in my project. Thank you for your time. Suggestions are welcomed. Regards, Manjunath _______________________________________________ http://www.opencores.org/mailman/listinfo/usb
-- Thanks & Regards, CH. Sarath Chandra Systems Engineer Reinfold Physical Innovation Labs #602 6th Floor, Supath Tower, Opp Ras Ranjan, Vijay Cross Road, Navarangpura, Ahmedabad – 380 009 India Mob: +91-9725258259 Ph: 079-30025747,30005747,40045747 http:// www.reinfold.net -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/usb/attachments/20080910/51f1a9e8/attachment.htm
Testbench code for usb2.0 core (wishbone compilant)
by Unknown on Sep 11, 2008
Not available!
Hi I have tested this core to a certain extent by developing TB in Vera and UTMI BFM's. I have stripped out the wishbone interface and designed an AHB interface and succesfully written to the memory arbiter of the core. Hope to be of some help for sharing some knowledge on this. Kindly do not ask for code to be sent to you. Regards Ananthu 2008/9/10 Sarath Chandra sarath at reinfold.net>
Hi Manjunath, Im also planning to test my usb2.0 core in future.however im still at the development stages of the core.im not developing it for wishbone compliant as you have mentioned in your query.i would be intrested in knowledge sharing about the core itself as im relatively new but i have to execute a project for my client which deals with USB2.0 based data transfer. please kindly acknowledge my request. Thanks in advance. On Wed, Sep 10, 2008 at 5:09 AM, manjunath_sirigiri at hotmail.com> wrote:
Hi all, I am working on the verilog testbench for the usb2.0 core (wish bone compliant). I need some clarifications about the testbench. 1) Do we need precise timing of the utmi signals as per the utmi xcvr specs. for watching the usb2.0 core to work 2) What is the procedure to setup the configuration of the usb2.0 at the first step. I am aware of the protocol of the usb2.0. How to convert them to utmi, wbc signals. 3) Has anyone already written the testbench for the usb2.0 core. Can anyone guide me in testing the core. I am working on a project that uses the usb2.0 core(software). I need to see it working working before I can interface it with other modules in my project. Thank you for your time. Suggestions are welcomed. Regards, Manjunath _______________________________________________ http://www.opencores.org/mailman/listinfo/usb
-- Thanks & Regards, CH. Sarath Chandra Systems Engineer Reinfold Physical Innovation Labs #602 6th Floor, Supath Tower, Opp Ras Ranjan, Vijay Cross Road, Navarangpura, Ahmedabad – 380 009 India Mob: +91-9725258259 Ph: 079-30025747,30005747,40045747 http:// www.reinfold.net _______________________________________________ http://www.opencores.org/mailman/listinfo/usb
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