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USB 1.1 PHY core - bit stuffing problem
by Unknown on Oct 22, 2008 |
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Hello,
I have a problem with the USB 1.1 PHY core - bit stuffing doesn't work correctly. In change history it says: "Revision 1.4 2004/10/19 09:29:07 rudi Fixed DPLL alignment in the rx_phy and bit stuffing errors in the tx_phy (if last bit bit was a stuff bit in a packet it was omitted). " I'm still getting this error. Does anyone know how to fix this? Maybe the file on the CVS is not the correct version? |
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USB 1.1 PHY core - bit stuffing problem
by Unknown on Oct 23, 2008 |
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Hi It is revision 1.5 and not 1.4
Dharmesh
On Wed, Oct 22, 2008 at 1:41 PM, Grzegorz Plebanski ygreg at ygreg.com> wrote:
Hello,
I have a problem with the USB 1.1 PHY core - bit stuffing doesn't work
correctly.
In change history it says:
"Revision 1.4 2004/10/19 09:29:07 rudi
Fixed DPLL alignment in the rx_phy and bit stuffing errors in the
tx_phy (if last bit bit was a stuff bit in a packet it was omitted). "
I'm still getting this error. Does anyone know how to fix this? Maybe
the file on the CVS is not the correct version?
_______________________________________________
http://www.opencores.org/mailman/listinfo/usb
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USB 1.1 PHY core - bit stuffing problem
by Unknown on Oct 24, 2008 |
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> Hi It is revision 1.5 and not 1.4
Transmitter module, which handles bit stuffing, is in file usb_phy/rtl/verilog/usb_tx_phy.v Latest revision of this file is 1.4, only usb_rx_phy.v is 1.5. |
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