Hi,
I am attempting to ad the usb2.0 module to minsoc. I am consulting usb_doc for the same.I have downloaded the USB1.1phy from opencores, and created the ssram using xilinx coregen. I instantiate ssram,usbf_top and usb_phy in minsoc_top.

1) USB_doc says that " The UTMI interface block, runs off the clock provided by the PHY".
Accordingly,the UTMI interface in the usb2.0 ip core has a phy_clk input port pin. But,there is no corresponding clk o/p from phy_core to connect to phy_clk input at UTMI. So which clock signal do I provide for UTMI? Is this mismatch arising becoz of different version of USB and phy core? If yes then is USB2.0phy available?

2)Which clock should I provide for the ssram? since in usb core no clock signal other than wb_clk, phy_clk is there, should I provide an external clock to ssram or one of these?

3)Should I add all of the following i/f signals in usb2.0 as i/p or o/p port in minsoc_top?
signals in usbf_top
wishbone i/f :dma_req_o, dma_ack_i, susp_o, resume_req_i,
utmi i/f :OpMode_pad_o, usb_vbus_pad_i,phy_rst_pad_o,
VControl_Load_pad_o, VControl_pad_o, VStatus_pad_i,
XcvSelect_pad_o, TermSel_pad_o,SuspendM_pad_o.

signals in usb_phy : phy_tx_mode .

thanx for any help
Mudit

Anyone who knows the solution,kindly reply .

Thanx
Mudit

Dear Mudit,

Fist of all USB2.0IP Core Phy_Clk(60 MHz for high speed) is driven by your physical chip. checkout your physical chip data sheet you will find 60 MHz clock out signal there. You need to provide appropriate input clock(depend upon phychip cristal) to physical chip Cristal to generate 60 MHz clock. This 60 Mhz physical chip output clock given to your USB2.0 IP Core.

==> You have to provide external clock to SSRAM using PPL or any-other source
==> you can take any number of signal in top file for just your debug purpose. but just take care that your UTMI signals properly connected with Physical chip.



Best Regards:

Ravi