from the usb 2.0 documentation that i read from opencores, i still blur about the input for it.. theoretically, the input is from an external phy. since now i am try to write out a test bench, i need to know the logic of the signal. can any1 point me to the right direction?

Hi,

USB2.o Device IP Core contain UTMI Interface. So if you want to start design Testbench then first of all Read UTMI+ Specification. In hardware this UTMI Interface signals is generated by UTMI PHY Chip. SO you have to design behaviour model of UTMI PHY for simulate USB2.o IP COre with UTMI Interface.

if you still have any doubt then let me know.


Best Regards:

R@vi