Hi,

I wanted to know whether RX Valid signal is always asserted in the next cycle after the assertion of RX Active signal. i.e., is there only a cycle delay between RX Active & RX Valid signal for all conditions.

The UTMI spec says it need not be, however all the timing diagrams in the UTMI spec has only a cycle delay between RX Active & RX Valid.

Can someone help me with this?

Regards,
Harish