Hello, I am doing bachelor's degree and new to the field of USB. I had to design a USB host controller for my project and so downloaded the IP Core from Opencores for USB 2.0 by Rudolf Usselmann. I have two questions:
1. In the IP there was an unconnected output named "rf_resume_req" from the
entity "usb_rf.v". I studied the verilog code and as I am more prominent user of VHDL, I could not get the exact use of this output but got that it is corresponding to some resume request from main CSR. But I couldnot find the main CSR in the Design. Please help.
2. In the design, is buffer memory the SSRAM? If not where is it situated?
3. In the buffers of endpoints, whether the data received is stored or the memory location of the buffer i.e the buffer pointer is stored and does the function controller updates the buffer pointer? If I am wrong at any point please tell me the exact function of buffer in endpoints.
4. I could not get the exact function of "Function Controller" in the design. I suppose its used for overall control of the USB device like decoding the requests which host sends, then putting all the blocks in different states according to work they have to perform and to direct the fetching of data from/to SSRAM.

I know it is a lot of information to ask for at once but i tried for lots of doubts by myself but couldnot figure out these problems. Also I designed my own IP core in VHDL but was a failure, Can someone tell where can i get help for designing VHDL IP CORE.

I have attached the documentation of the design and all the modules.
Thanks
Dixit Sethi