I'm trying to simulation "USB 1.1 PHY (VHDL)" (http://opencores.org/project,usb11_phy_translation) with the USB 1.1 Simulation (http://opencores.org/project,usb11_sim_model).

In the pdf doc t says

After a successful simulation run it is a good idee to rename the test log file Result.out so
that this file name matches that of the original test case file, e.g. tc_02.out for later reference.

But my simulation has not run succesfully. THe output I get is:
*****************************
* Results of tc_02.vhd *
*****************************

Test_No 10
Reset completed, initializing
Test_No 20
1866 ns Send Setup: Address 0x00, Endpoint 0x0, CRC5 0x02
4890 ns Send Data0 0x80 0x06 0x00 0x01 0x00 0x00 0x40 0x00 0xDD 0x94
13642 ns Recv ACK
15562 ns Send IN-Token: Address 0x00, Endpoint 0x0, CRC5 0x02
18938 ns Recv Data1 0x12 0x01 0x10 0x01 0x02 0x00 0x00 0x40 0x9A 0xFB 0x9A 0xFB 0x20 0x00 0x00 0x00
29818 ns ..... 0x00 0x01 0xB4 0x2C
33610 ns Send ACK
35306 ns Send OUT-Token: Address 0x00, Endpoint 0x0, CRC5 0x02
38330 ns Send Data0 0x00 0x00
41690 ns Recv ACK
Test_No 30
43530 ns Send Setup: Address 0x00, Endpoint 0x0, CRC5 0x02
46554 ns Send Data0 0x00 0x05 0x03 0x00 0x00 0x00 0x00 0x00 0xEA 0xC7
55386 ns Recv ACK
57226 ns Send IN-Token: Address 0x00, Endpoint 0x0, CRC5 0x02

This is only the first part of the usb_tc_02.out.
I also get a lot of "Error: Assertion violation", and I don't know where this error message comes from (from model sim maybe?).