I am using isp1763 USB controller on my board. It's configured in SRAM 16bit mode. The chip doesn't have any byte enable pins so I am using native alignment. Currently I am having trouble with the Avalon slave interface that implemented. For some reason when I dump memory at the base address, I see the values are at an offset of 4x (this is because of native alignment) and they repeat (not sure why?). The interface has:
1. cs_n
2. reset_n
3. read_n
4. write_n
5. Interrupt
6. address (16 downto 0)
7. read/write data (15 downto 0)

So my question here is:
1. Why do the values repeat?
2. Is it possible to use dynamic addressing without byte enable pins on the USB chip?
3. Has anybody implemented interface with ISP1763? If yes, would you be willing to share the verilog/vhdl file?

Appreciate any response on this.

Thanks

I was able to figure out some of the answers:
ISP1763 uses byte addressing and I am using it in 16bit mode. If address alignment is dynamic, address pin A0 of FPGA need to be connected to A1 on USB controller. For native alignment it has to be shifted one more bit.