OpenCores
no use no use 1/1 no use no use
USB 3.1
by logicatoms on Aug 25, 2015
logicatoms
Posts: 5
Joined: Apr 26, 2015
Last seen: Sep 8, 2016
1. what are all the sufficient documents to be read to implement
(Documents/Specification in addition to USB 3.1 spec from usb.org)

a USB 3.1

1.Device controller
2.Hub Controller
3.Host Controller


2. Essential patents to license to implement USB 3.1 specification



Thanks,
Simha.


RE: USB 3.1
by dgisselq on Aug 28, 2015
dgisselq
Posts: 246
Joined: Feb 20, 2015
Last seen: May 12, 2020
There exist some common interface formats for interfacing with a USB device. I think it would be valuabel for any core handling the low levels of a USB interface to talk to the next level up using a common interface format. You may wish to look up what interfaces various USB peripherals use and see if you can match those, for example.

Dan
RE: USB 3.1
by ridha.ghayoula on Aug 25, 2017
ridha.ghayoula
Posts: 1
Joined: Jul 22, 2017
Last seen: May 27, 2020
Design synthesizable USB 3.0 using Verilog HDL and simulate design using Cadence
USB_3_Final.pdf (1151 kb)
RE: USB 3.1
by venkateshraju39 on Feb 23, 2018
venkateshraju39
Posts: 4
Joined: Jul 30, 2016
Last seen: Oct 29, 2018
Design synthesizable USB 3.0 using Verilog HDL and simulate design using Cadence
USB_3_Final.pdf (1151 kb)

If your planning to develop RTL for USB 3.0 and USB3.1 give some inputs i can join with you.
i have working experience in the USB protocol layer and link layer.
RE: USB 3.1
by alidehghannayeri on Aug 6, 2019
alidehghannayeri
Posts: 1
Joined: Jul 30, 2019
Last seen: Aug 6, 2019
Hello, I work in a dataLogger project.
We need USB 3.0 -3.1 IP Core for Spartan6
to connect FPGA to pc.
I have searched a lot of sites but every time I faced problems.
I look forward to hearing from you.
please answer me as soon as possible.
"ali2dehghan137777@gmail.com"
no use no use 1/1 no use no use
© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.