LogicProbe :: Overview

Project maintainers


Name: logicprobe
Created: Dec 20, 2013
Updated: Apr 22, 2017
SVN Updated: Nov 13, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

★ Star 0 you like it: star it!

Other project properties

Category: Testing / Verification
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD

Current stable version

Moved to GitHub.


LogicProbe is a very simple logic analyzer which can be run on
an FPGA in parallel with the "device under test". The analyzer
has a width of 128 data channels, and is 512 samples deep. It
has a trigger (i.e., it starts catching the channels when this
signal got active once), and a sample enable (i.e., it does only
sample the channels when this line is 1). It uses the block RAM
on the FPGA to store the samples in real-time. When the sample
buffer is full, it begins to transmit the samples through a UART
(also included in the code) over the serial line to a PC where
the sample values are stored in a file. A simple listing program
allows to view the samples as hexadecimal values.

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