OpenCores

AC 97 Controller IP Core :: Overview

Details

Name: ac97
Created: Sep 25, 2001
Updated: Jul 11, 2011
SVN Updated: Jul 12, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

★ Star 1 you like it: star it!

Other project properties

Category: System controller
Language: Verilog
Development status: Stable
Additional info: none
WishBone compliant: Yes
WishBone version: n/a
License:

Description

This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.

Features

- AC97 Revision 2.2 Compliant
- Variable and Fixed Sample Rate Support, up 48 kHz
- 16, 18 and 20 bit Sample Size Support
- 6 Channel Surround Sound Support
- Stereo Input channel Support
- Mono Microphone Channel Support
- External DMA Engine Support
- WISHBONE SoC host Interface

Status

- 8/2/2001 New Directory Structure ! We have agreed on a common directory structure at OpenCores.
- The AC97 Core is Done !
- I will post a message to cores@opencores.org each time I have an update

Change log

- 8/2/2001 RU New Directory Structure Update
- 19/5/2001 RU First Release
- 11/5/2001 RU Added link to the spec.
- 3/5/2001 RU Initial web page



This IP Core is provided by:

www.ASICS.ws - Solutions for your ASIC/FPGA needs -

© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.