TIME SLOT INTERCHANGE DIGITAL SWITCH
This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.
| Date | File | Description |
| 2004-05-10 18:36 | TDM_Switch_DS.pdf | TDM_Switch_DS.pdf |
| 2003-10-25 09:50 | ModelSim_Edition.exe | Self extracting (RAR) archive of this project for ModelSim behavioral simulation |
| 2003-08-24 11:01 | stream_7.dat | Data for input stream 7 |
| 2003-08-24 11:00 | stream_6.dat | Data for input stream 6 |
| 2003-08-24 11:00 | stream_5.dat | Data for input stream 5 |
| 2003-08-24 11:00 | stream_4.dat | Data for input stream 4 |
| 2003-08-24 11:00 | stream_3.dat | Data for input stream 3 |
| 2003-08-24 10:59 | stream_2.dat | Data for input stream 2 |
| 2003-08-24 10:59 | stream_1.dat | Data for input stream 1 |
| 2003-08-24 10:59 | stream_0.dat | Data for input stream 0 |
| 2003-08-24 10:59 | map.dat | Data file for connection memory (line 1-256) and frame delay registers (line 257-264) |
| 2003-08-24 10:58 | testbench_top.v | Testbench for top module |
| 2003-08-24 10:57 | tdm_switch_top_timesim.sdf | SDF annotation file for “tdm_switch_top_timesim.v” netlist |
| 2003-08-24 10:43 | tdm_switch_top_timesim.v | Post Place and Route Verilog netlist file created by Xilinx ISE 5.2i for Concept NC-Verilog simulator |
| 2003-08-24 10:42 | tdm_switch_b.v | Top module of TDM Switch for behavioral simulation |
| 2003-08-24 10:40 | tdm_switch_top.v | Top module of Time Slot Interchange Digital Switch |
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