This page contains files uploaded to the old opencores website as well as images and documents intended for use on other pages in this project. If you want to download this project or browse its svn, you can do so at the overview-page.

Date File Description
TDM_Switch_DS.pdf TDM_Switch_DS.pdf
ModelSim_Edition.exe Self extracting (RAR) archive of this project for ModelSim behavioral simulation
stream_7.dat Data for input stream 7
stream_6.dat Data for input stream 6
stream_5.dat Data for input stream 5
stream_4.dat Data for input stream 4
stream_3.dat Data for input stream 3
stream_2.dat Data for input stream 2
stream_1.dat Data for input stream 1
stream_0.dat Data for input stream 0
map.dat Data file for connection memory (line 1-256) and frame delay registers (line 257-264)
testbench_top.v Testbench for top module
tdm_switch_top_timesim.sdf SDF annotation file for “tdm_switch_top_timesim.v” netlist
tdm_switch_top_timesim.v Post Place and Route Verilog netlist file created by Xilinx ISE 5.2i for Concept NC-Verilog simulator
tdm_switch_b.v Top module of TDM Switch for behavioral simulation
tdm_switch_top.v Top module of Time Slot Interchange Digital Switch
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