8051 core

When the jbc instruction is executed, it is only supposed to clear the one bit that was being tested. Instead, it writes to the entire byte, setting some bits and clearing others. The correct data to write is there, but in the wrong cycle. I patched this behavior in my simulation by detecting this opcode, grabbing the correct write data, which is there one cycle before the actual write, then I let the write happen, and one cycle later I set that RAM location to the value that I saved. When I add this workaround, all of a sudden my simulation starts to run correctly. So either someone needs to fix the jbc op code implementation or you will want to avoid using that instruction when using this rtl. Bob