jakas

Teran, Simon

8051 core

the upper 8 bits of the address on movx instrs should come from P2, but they are all 0's instead, unless dptr is being used.   I changed the memory interface to use P2 and now my simulation is running much better.
Bob

movx upper addr wrong

In the Intel 8051, when a movx is used to access external RAM, the P2 port supplies the upper 8 bits of the address.   When the dptr is used, all 16 bits come from the dptr.   In this model, P2 comes out separately, and the upper 8 address bits were all 0's on movx accesses.   I changed the memory interface block to use the P2 value instead.   My simulation is working better now.  Seems there are some other bugs.   Maybe I haven't hit them yet...

Movx upper address

When the jbc instruction is executed, it is only supposed to clear the one bit that was being tested.  Instead, it writes to the entire byte, setting some bits 
and clearing others.   The correct data to write is there, but in the wrong cycle.  I patched this behavior in my simulation by detecting this opcode, grabbing the correct write data, which is there one cycle before the actual write, then I let the write happen, and one cycle later I set that RAM location to the value that I saved.   When I add this workaround, all of a sudden my simulation starts to run correctly.  So either someone needs to fix the jbc op code implementation or you will want to avoid using that instruction when using this rtl.   Bob

definite bug with jbc

I am running a simulation with the latest version of the CPU and it seems that the jbc instruction can affect other bits in the same byte as the one that is being tested and cleared.  I am using Modelsim with my own test bench, based on the oc8051 tb file.   

          Bob

possible bug with jbc instruction

at the file "oc8051_sp.v"

output [7:0] sp_out, sp_w;

reg [7:0] sp_out, sp_w;

always @(sp or ram_wr_sel)
begin
//
// push
  if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
  else sp_w = sp;

end

but seem possible the "sp_w" is never used.

unuseing signal

Hello, i'm trying to simulate the oc8051 with external rom (oc8051_xrom.v) adding delays, but I achieve to simulate when parameter DELAY = 0, however, i don't achieve to simulate when i put the value 5 in parameter DELAY. 

Is there some problem to achieve this???? I need some specific core if i want to add it? 

thanks, for yo replay

xrom

Hello, I'm working on with this processor and I saw two module definition that not matches.

The firt one is the oc8051_rom for xilinx (path5 --> /trunk/syn/src/verilog)
The module definition is the next :

module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

and the module instation that belong on the oc8051_top.v is the next:

   oc8051_rom oc8051_rom1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
		       .ea_int(ea_int),
		       .addr(iadr_o),
		       .data_o(idat_onchip)
		       );

I'm little confused because I don't where the pipeline happens. If i add a rom (with the right capacity), It is enough to work properly?

thanks for your replay

oc8051

Tools: Compiler ISE Suite 11.5
       Simulator: ModelSim SE 6.5c
Device: Xilinx Virtext 5

The core works perfectly at Behavioral simulation but it works incorrectly at Post-Route simulation with incorrect output signals (wishbone interface for data memory and address for the instruction memory).
The implementation also works incorrectly in the FPGA Virtext 5 chip.

8051 works incorrectly at Post-Route simulation

Hi,

I could not find generic_dpram.v.
Anybody knows where it is?

Thanks,
KS

generic_dpram.v'

Hi

I tried "run" script under the rtl_sim/run/.
BTW thter is missing file.
I got a message like below.
"ncvlog: *E,COFILE: cannot open source file '../../../../common/generic_memories/rtl/verilog/generic_dpram.v'."
Do you know where is generic_dpram.v.

Thanks,
KS

Untitled bug

I am using the Xilinx ISE WEBPack tools. I can not get the tools to see the
module oc8051_ram_256x8_two_bist.v

Am I missing something?

John

Cound not find module/primitive

Is there documentation on software devolopment with OC8051, bascally going from C(or asm) program to HEX to IN to verilog rom files, and the tools used in the translation process,  compiler? assember?


Is this program currently under acitive devoplment?

Browse

8051 core