8051 core

Tools: Compiler ISE Suite 11.5 Simulator: ModelSim SE 6.5c Device: Xilinx Virtext 5

The core works perfectly at Behavioral simulation but it works incorrectly at Post-Route simulation with incorrect output signals (wishbone interface for data memory and address for the instruction memory). The implementation also works incorrectly in the FPGA Virtext 5 chip.

Please verify the stb/cyc with "nop" operation at Post-Route simulation. Then, the write instruction to the ports, especially, port 0.