8051 core

Hello, I'm working on with this processor and I saw two module definition that not matches.

The firt one is the oc8051_rom for xilinx (path5 --> /trunk/syn/src/verilog) The module definition is the next :

module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);

and the module instation that belong on the oc8051_top.v is the next:

oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(iadr_o), .data_o(idat_onchip) );

I'm little confused because I don't where the pipeline happens. If i add a rom (with the right capacity), It is enough to work properly?

thanks for your replay

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Hello, I also don't know how to add the quartus ii rom core. because i need to read three Bytes in one clock cycle,I don't kown how to realize it by quatus ii rom core. thank you !