8051 core

Hi,

I could not find generic_dpram.v. Anybody knows where it is?

Thanks, KS

The missing module is a standard FPGA RAM component use the FPGA manufacturers tools to build the RAM and rename the ports for the instance if necessary.

Since the component is manufacturer specific, and the RTL is from 2001, this code would not be compatible with contemporary devices.

Otherwise you can write generic RAM code and let the FPGA tools recognize it as a memory. There are many online Verilog tutorials you can use.

Thanks a lot for this comment! Created altera ram 2 port megafunction and compilation was finally successful!