Advanced Debug System

Rate limiting was removed as of bug 535, (Oct 01, 2009) as the OS blocks I/O calls until inb or outb completion.

However I have found that this causes my Xilinx PC3 clone to fail despite it working ok in Xilinx Impact 12.1 (where it is limited to a 200 kHz TCK).

With a simple test program I have recorded a maximum parallel port output rate of 667 kHz.

Xilinx document XTP029 (www.xilinx.com/support/documentation/user_guides/xtp029.pdf) explains that TCK rate is entirely defined by the host system's parallel port speed. Hence the fault is with the JTAG programmer.

However, some option to limit the parallel port data rate would be useful to those of us using cheap programmers.

The overhead of usleep(1) seems to slow the clock to tens of kHz so I have worked around this by simply tripling each occurrence of outb/inb calls, bringing TCK to a manageable 222kHz (ugly, I know).

Thanks,

Andrew 0xADF

Timer-based waits added in SVN rev. 55.