Sbox is a major part of AES. Sbox can be implemented using look up tables or in combinational logic, using composite field. This project aims at implementing AES using composite field. The advantages of this type of implementation is low area and Higher speeds, which can be achieved using pipeling. Where as AES using LUT's have restrictions on pipelining (LUT's bottlenect the pipelineing speed).
- Written in Verilog
- Throughly tested
- Post "place and route" netlist tested on Vertex 1000E fpga and ST12 standard cell library.
- status1 Project opened on 19th July, 2005.
- status2 files updated to test repository undername "FastAES".
- status2 Finished.