Amber ARM-compatible core

The V flag gets set by TST and TEQ. The manual says only the N,C and Z flags are affected. Sample code below..

;; set the flags 
TEQP	PC,#&90000000
;; do the test
MOV	R1,#0
TST	R1,#0

;; Flags should be 5 here (Z and V)
;; on Amber the flags are 4 (Just Z)
MOVVC	R0,#0
MOVVS	R0,#1

And the same test also works for TEQ

;; set the flags 
TEQP	PC,#&90000000
;; do the test
MOV	R1,#0
TEQ	R1,#0

;; Flags should be 5 here (Z and V)
;; on Amber the flags are 4 (Just Z)
MOVVC	R0,#0
MOVVS	R0,#1

In both cases the V flag is reset to zero instead of being preserved.

I resolved this in my local copy by making the decode unit emit a o_status_bits_flags_mask, this mask is usually 4'hF but for instructions that want to not set certain flags it sets those bits low. This lets me do this for other instructions later if find any with odd edge case requirements. Patch is available from my me via my opencores email on request.