There is a combinatorial feedback loop in a25_decode.v (decode stage of the 5-stage processor core).
Warning message from Xilinx: WARNING:Xst:2170 - Unit a25_decode : the following signal(s) form a combinatorial loop: rds_use_rs, instruction_valid_interrupt_AND_17_o, rs_sel_nxt3_load_rd_d1_nxt3_equal_153_o1, control_state4_conflict_AND_131_o, instruction15_mtrans_reg13_mux_63_OUT<0>, rs_sel_nxt<0>, o_user_mode_regs_store_nxt, rs_sel_nxt3_load_rd_d1_nxt3_equal_153_o, rs_conflict1, o_conflict, interrupt.
Traced back to RTL (line numbers refer to a25_decode.v):
1) Line 693: interrupt = f (conflict): assign interrupt = next_interrupt != 3'd0 && next_interrupt != 3'd7 && // SWI next_interrupt != 3'd6 && // undefined interrupt !conflict ; // Wait for conflicts to resolve before // triggering int 2) Line 541: conflict = f (conflict1): assign conflict = conflict1 || conflict2;
3) Line 535:conflict1 = f (rs_conflict1): assign conflict1 = instruction_valid && (rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 || stm_conflict1a || stm_conflict1b);
4) Line 525: rs_conflict1 = f (rs_valid): assign rs_conflict1 = instruction_execute && rs_valid && ( load_rd_d1_nxt4 && rs_sel_nxt == load_rd_d1_nxt3:0 );
5) Line 516: rs_valid = f (rds_use_rs): assign rs_valid = rds_use_rs;
6) Line 456: rds_use_rs = f (interrupt): assign rds_use_rs = (type == REGOP && !instruction25 && instruction4) || (type == MULT && (control_state == MULT_PROC1 || control_state == MULT_PROC2 || instruction_valid && !interrupt )) ;
Combinational loop removed.