Amber ARM-compatible core

I went to verify the latest sources and I noticed that in the latest SVN version there has been some re-factoring of my patch (fair enough - it was a bit rough). It seems this breaks thousands of fuzz test results though :(

The same tests pass when pointed at the unrefactored sources. :/

bics r4, r12, #0x63 ... loop: 0 instruction: e3dc4063 Failed. errors: expected,actual,bitwise difference r4(0x738f3690,0x72b1479c,0x013e710c) r15(0x2c001011,0x2c001013,0x00000002)

initial: r0=0x7f68da85,r1=0x0f09f350,r2=0x24560884,r3=0x720a8380,r4=0x2b4886dd,r5=0x42ab98e5,r6=0x533f02ea,r7=0x33231392,r8=0x2b9bab45,r9=0x128241dd,r10=0x4e49468a,r11=0x2bebe2eb,r12=0x72b1479f,r13=0x1bfeffa1,r14=0x25006b80,r15=0x2eb73661,r8_firq=0x6a180405,r9_firq=0x37848102,r10_firq=0x2d0261dd,r11_firq=0x396443e2,r12_firq=0x738f36d1,r13_firq=0x5853619a,r14_firq=0x100d0c38,r13_irq=0x334b0228,r14_irq=0x650f8cff,r13_svc=0x2932006f,r14_svc=0x139fc17c,

arcem: r0=0x7f68da85,r1=0x0f09f350,r2=0x24560884,r3=0x720a8380,r4=0x738f3690,r5=0x42ab98e5,r6=0x533f02ea,r7=0x33231392,r8=0x2b9bab45,r9=0x128241dd,r10=0x4e49468a,r11=0x2bebe2eb,r12=0x72b1479f,r13=0x1bfeffa1,r14=0x25006b80,r15=0x2c001011,r8_firq=0x6a180405,r9_firq=0x37848102,r10_firq=0x2d0261dd,r11_firq=0x396443e2,r12_firq=0x738f36d1,r13_firq=0x5853619a,r14_firq=0x100d0c38,r13_irq=0x334b0228,r14_irq=0x650f8cff,r13_svc=0x2932006f,r14_svc=0x139fc17c,

amber: r0=0x7f68da85,r1=0x0f09f350,r2=0x24560884,r3=0x720a8380,r4=0x72b1479c,r5=0x42ab98e5,r6=0x533f02ea,r7=0x33231392,r8=0x2b9bab45,r9=0x128241dd,r10=0x4e49468a,r11=0x2bebe2eb,r12=0x72b1479f,r13=0x1bfeffa1,r14=0x25006b80,r15=0x2c001013,r8_firq=0x6a180405,r9_firq=0x37848102,r10_firq=0x2d0261dd,r11_firq=0x396443e2,r12_firq=0x738f36d1,r13_firq=0x5853619a,r14_firq=0x100d0c38,r13_irq=0x334b0228,r14_irq=0x650f8cff,r13_svc=0x2932006f,r14_svc=0x139fc17c,

I will keep checking.

Hmmm it seems like its actually to do with the CPU mode. Odd. Will investigate more.

My mistake. close this.