Amber ARM-compatible core

Hello,

I'm trying to use interrupt controller with amber23.

I use whole source code you uploaded. So interrupt controller I use is included in hw source code.

I have few questions. First, does your interrupt controller can control nested interrupts? Second, like I said, I'm trying to use interrupt feature. But there are too less information about amber23 processor. Is there any reference design, code or documents?

I'm really digging to have processor working.

Thanks for all your works. Dave. Thanks.

I'll add more questions. How can I clear irq_mask?

In code, status_bits_irq_mask_nxt is always 1'd1;

so I think irq couldn't be cleared.

Thanks.

ARM core provides 2 interrupt input pins irq and firq (fast). The idea is that irq is for relatively slow and complex interrupts, so its cpu mode provides a big set of registers. firq is intended for short, high frequency interrupts so it provides only a couple of registers. irq and firq both provide a stack pointer.

The amber system also had a secondary interrupt controller connected to the irq input. That allows multiple sources to generate interrupts. You can see simple example code using it in boot-loader-ethmac/start.S, service_irq routine.

It is quite easy to write interrupt routines that allow 2 levels of nesting. An firq interrupt can happen during an irq service routine. They have their own stack pointers so easy to maintain context.

More levels of nesting is possible but it makes the interrupt routine more complex. You would need to save context of interrupt that just occurred and then enable the interrupts with higher level of priority. You might need different stacks per interrupt source depending on how complex the service routine is. Many different ways to do this.

Correct the status_bits_irq mask in decode module is always 1. Its corresponding wen bit can be a 1 or 0. The value gets applied in the execute module depending on other stuff, so it works correctly AFAIK.

Solved.

Thanks.

This is cleared