Herveille, Richard

OCIDEC (OpenCores IDE Controller)

Hi,

I am interested in udma support. I would like to know when do you plan to release it.

thanks,

Sebastien

OCIDEC-4 / UDMA

I am having some problem to speed up the rate of this controller. I tried option such as changing the timing register value, giving a 66 Mhz clk instead of 33 Mhz but it doesnot work for some reason. Does anyone has a testbench or sufficient documentation to show the read trasfer rate boosting mechanism.

Thanks,
Raj

PIO Mode 4 speed

I found that the read data is sampled one clock cycle too late.

The foundation for this behaviour is made in atahost_pio_tctrl.vhd.  In process T2proc, DIOR follows IORDY_done after one cycle.  In process gen_dstrb, dstrb follows IORDY_done after one cycle, too.  That is, the external read cycle terminates at the rising edge of dstrb.

The bug is caused then in atahost_pio_actrl.vhd, process gen_PIOq, where DDi is synchronously registered when dstrb is active, ie one clock cycle after the external read cycle has been signalled as terminated.

Marc

Read data sampled too late

I found that CS may be released too early, ie before Teoc is over.

This is caused in atahost_pio_tctrl.vhd by assigning done <= T4done;

When changing it to done <= Teoc_done, the problem goes away.

Marc

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OCIDEC (OpenCores IDE Controller)