Attiny Atmega Xmega core

io/twi_s.v references a PULLUP:

PULLUP PULLUP_scl_inst (
.O(scl)  // 1-bit output: Pullup output (connect directly to top-level port)
);
PULLUP PULLUP_sda_inst (
.O(sda)  // 1-bit output: Pullup output (connect directly to top-level port)
);

How is that supposed to be implemented?

My synthesis complains:

Error	2019990	Synthesis	ERROR - CG389 :"/home/j/my_designs/mega_avr/source/impl_1/twi_s.v":322:7:322:21|Reference to undefined module PULLUP [twi_s.v:322]	

PULLUP are platform dependent configured at build time for LATTICE FPGA's, don't know on Altera/Intel ones, the PULLUP from design match XILINX Artix7 FPGA's, Artix7 have dedicated modules for PULLUP's.