Simple AXI4-Lite bridges for IPbus and Wishbone

According to thre AXI4 specification: http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf page A3-36 & A3-37, "On master and slave interfaces there must be no combinatorial paths between input and output signals." Current implementation boosts performanced by violating that requirement. It is to be investigated whether we can comply to requirement to register all output signals without loosing clock cycles.