Simple AXI4-Lite bridges for IPbus and Wishbone

Project maintainers

Details

Name: ax4lbr
Created: May 15, 2016
Updated: Jun 7, 2016
SVN Updated: May 15, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

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Other project properties

Category:System on Chip
Language:VHDL
Development status:Alpha
Additional info:
WishBone compliant: No
WishBone version: n/a
License: Others

Description

This project provides very simple bridges from AXI4-Lite interface to IPbus and Wishbone buses.
The design has been tested on Xilinx Zynq (Z-Turn board with xc7z020 chip) and Altera Cyclone V (DE0 NANO SoC board with 5CSEMA4U23C6).

The complete demo designs based on those bridges for Z-Turn board, together with scripts for building the Vivado project may be found at https://github.com/wzabvextproj in version_2 directory.

Implementation of Wishbone bridge is very limited. Currently it supports only "Classic Standard" mode.

LICENSE
The project is licensed under Creative Commons CC0 license or as PUBLIC DOMAIN (whatever is better suited for you).