AXI4 Transactor and Bus Functional Model

Aug 30, 2015	Design has been used in a few projects.	kho, daniel
Apr 19, 2014	Description updated on the use of coverage-driven constrained random verification techniques.	kho, daniel
Apr 7, 2014	Added coverage-driven constrained random testcases.	kho, daniel
Mar 10, 2014	Updated timing report to latest report from TimeQuest STA.	kho, daniel
Jan 20, 2014	Optimised design to be smaller, faster, and more pipelined.	kho, daniel
Oct 7, 2013	Added scopeshots from ModelSim and Quartus SignalTap.	kho, daniel
Sep 18, 2013	Synthesizable design of basic AXI4-Stream interface completed. Design verified on an Altera FPGA.	kho, daniel
Sep 10, 2013	FPGA proven on Cyclone III.	kho, daniel
Jun 25, 2013	Described plan to include OSVVM intelligent testbench.	kho, daniel
May 29, 2013	Introduced several minor updates to enhance clarity.	kho, daniel
May 28, 2013	Added simulation instructions.	kho, daniel
May 28, 2013	Simulation of AXI4-Stream write done.	kho, daniel

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