Open Design Prototype Board

Introduction

All electronics designers, students and researchers are always trying to test their ideas and check its performance before punishing it. Several kinds of test prototype boards are used for this purpose. Usually these boards are either very expensive and has either more or less features than what the designer need. For this reason the idea of designing a simple and open design board is going to be available for anyone for almost nothing and he/she can customize it for his/her specific needs. The design of this board is intended to be an open design and to use free and open design tools in order to make it available to large number of designers around the world.

Objective

This project is intended to:

• To prove the open hardware design concept.
• To make a simple and easy platform for testing small digital cores.
• To Implement, test and define free based tool design flow.
• To build simple generic prototype board for digital designs

---

Design License

This project is going to be a free hardware design. It uses GNU license style for hardware. As a result this project is going to use the OpenIPCore license. You can check the draft copy of this license at OpenIPCore License page

---

Design Flow

This project can be divided into two parts. The board design and the cores design.
Of course, anyone can use the commercial tools to design and implement this project, but my objective is to build it using only free tools "GNU and non-GNU". so in this article I'll describe only the Free "hopefully Open" design flow.

Board design
The board design flow can be done through four steps:

• Block Diagram design: This can be drawn either by Xfig or gimp or any other gnu graphic tool
• Schematic entry: gschem from gEDA tool is the best schematic design entry tool although it still need some extra features and lot of symbols that anyone can draw by himself
• Netlist extraction: Also the gnetlist from gEDA tool can be used to capture the schematic design and extract it into several netlist file format "tango" is one of them. This tool is still under development
• Layout design: The gpcb tool from gEDA does not reach a good level of development so it can not be used for now "may be later". PCB interactive printed circuit board design by Thomas Nau can be used instead.
• Board implementation: This is the final step in the design where the designer should work himself to produce his board

Cores design
Design Flow

• Design Entry:
  • VHDL or Verilog designs can use emacs or Xemacs VHDL or Verilog modes.
  • Block diagram to HDL based designs can use VGUI
  • VHDL state diagrams can use xfig and BRUSE Y20 tool
• Simulation:Simulate it using Savant
• Synthesis:Synthesis using Alliance or webfitter
• PPRusing Xilinx webfitter
• ProgrammingDownload the JEDC file through the PC parallel port ot the board using Xilinx tools

---

Testing and Debugging the designn
One of the most important factors in hardware design is the testing and debugging of the design's physical implementation. Scopes, logic analayzers and DMMs are the most important devices that are used to debug hardware. In our project we are using the free approach, so we have to keep using this approach even in the debugging hardware.
Xscope is a PC based open-design scope. The whole design -including documentation, schematics, layout and the software are available from the xscope site.
Since the Xscope software is available, DMM can be easly implemented by enhancing the software and adding small circuits to measure the current and the impedance.
Logic analayzer can be implemented by the designing a small core for the CPLD and download it to the board itself.

---

System Description

Board block diagram
The system is composed of 6 main blocs:

• JTAG interface: The JTAG interface is used to program the CPLD on-board. This interface is connected to the JTAG pins on the XC9500 CPLD. From the other side, it is connected to the computer parallel port through a special circuit and a cable. This circuit and cable are documented by Xilinx. The software programmer from xilinx communicates with the CPLD and program it over this cable. This cable is used only during the configuration of the chip. The JTAG circuit is going to be as the Xilinx parallel cable and is going to be implemented on board and connected only through wires to the PC parallel port.
• External Interfaces:The Board has about 64 IO "TBD" pins to the external world. These pins are mapped to two connectors, the standard PC parallel Port connector and the reset of the pins go to another connector. The parallel port interface connector is used to simplify the interface to the PC, yet available to any other applications. Each connector has dedicated reset and clock pins. May be we are going to use some kind of isolation between the system and external devices to increase the protection against ground loops. This may be achieved through opto-couplers
• On board IO pins: The board has also on board IO pins. 10 pins are connected to on-board LEDs and 10 pins are connected to on-board dip switch. The number 10 is chosen because most applications uses 8-bit data and we add 2 extra control pins. These pins share the same IO pins on the external interface through special circuit.For example the on-board display leds are connected directly between the I/O pad and the connector and they can be considered as output indicators. While the Dip switches are connected through circuit and these are considered as inputs to the system
• Clocks:
• Reset circuit:
• Power supply:The board requires 5 and 3.3v volt regulated power supply. This is going to be achieved by using a 5v DC supply via a power connector. The 3.3v supply is an optional for those designs that need 3.3 IO pins. In this case a jumper will be used to switch between 5v and 3.3 v that applied to CPLD pins no. 22 and 64. The maximum current that is going to be consumed is "TBD".

---

CPLD Pin assignment

Clocks

• GCK1: goes from the on board oscillator
• GCK2: goes from the external board interface
• GCK3: goes from the PC parallel port interface

IO pins

• 17 IO pins go to the PC parallel Port interface, including CLK and Reset signsl
• 53 IO pins go to the External interface connector, including clk and reset signals
• 10 IO pins are shared with the External interface connector and connected to 10 LEDs
• 10 IO pins are shared with the External interface connector and connected to 10 DIP switches

Global Reset GSR pin is connected to a reset source select circuit. This circuit selects the reset either from the the external interface line, PC parallel port line or on board push button switch.This circuit is a hard wired circuit and can be implemented by jumper select. Note: the real pin mapping (i.e. pin to pin ) is going to be determined later.

---

Schematic Design

TBD

gschem symbols

• XC95108-pc84. Download Symbol

---

Board Mechanical Design

TBD

---

Layout Design

TBD

---

Bill Of Materials

• DB 25 PC Parallel Port connector.
• XC95108-PC84 xilinx CPLD
• 11 LEDs 10 for data and one for power
• 10 Dip switches
• 5 volt power regulator :TBD

---

Component selection guide

• XC95108-PC84 xilinx CPLD

Macro cells = 108 cells
Registers = 108 register
Usable gates = 2400 gates
I/O pins = 69 pins
Total Pins = 84 pins
Package = PLCC
Voltage supply = 5v
Cost = 13$

---

Contact us:

You can send your comments to:

• khatib@opeip.org
• m_tirhi@hotmail.com

You can also send your comments toopenip@egroups.com

---

References tools and links

• Xfig Home page
• gEDA tools home page
• PCB interactive printed circuit board design home page
• Xilinx Home page
• Xilinx Xpresso tools Home page
• XC9500 data sheet
• Xemacs Home page
• FreeHDL Home page
• Alliance Home page
• VGUI block to hdl converter home page
• brusey20 state machine to VHDL converter home page
• Savant VHDL simulator Home Page
• Xscope home page