BTCMiner - Open Source Bitcoin Miner

I am getting the below Error Message on Xilinx Vivado Verilog Coder on all of the below lines. Error: Syntax Error near "["

		data15_p1 <= `S1(S[i-1].data[`IDX(15)]); //3 
		data15_p3 <= ( ( i == 1 ) ? `S1( S[i-1].data[`IDX(14)] ) : S[i-1].data15_p2 ) + S[i-1].data[`IDX(9)] + S[i-1].data[`IDX(0)]; // 3
		data[`IDX(15)] <= `S0( data_buf[`IDX(1)] ) + data15_p3; // 4
		t1 <= `CH( S[i-1].state[`IDX(4)], S[i-1].state[`IDX(5)], S[i-1].state[`IDX(6)] ) + `E1( S[i-1].state[`IDX(4)] ) + S[i-1].t1_p1;	// 6
		state[`IDX(0)] <= `MAJ( state_buf[`IDX(0)], state_buf[`IDX(1)], state_buf[`IDX(2)] ) + `E0( state_buf[`IDX(0)] ) + t1;		// 7