Codezero OpenRISC Port


Name: c0or1k
Created: Apr 19, 2010
Updated: Jun 15, 2010
SVN Updated: May 5, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: GPL



The aim of the project is to port and maintain Codezero microkernel to the OpenRISC 1000 family.

L4 microkernel architecture

Codezero is a new L4 microkernel that has been written from scratch, following the latest development and research principles on microkernel design. It is a modern microkernel implementation that provides capabilities for virtualization and implementation of native OS services.

Design principles

Codezero and L4 line of microkernels are founded on a few fundamental design principles. The primary principle is that only the most fundamental and abstract software mechanisms are incorporated into the microkernel, ruling out any policy from the implementation. Codezero implements only the mechanisms to manage threads, address spaces, and the communication mechanisms between them.


In relation to its main founding principle, the microkernel becomes simple, abstract, and flexible. Due to its abstract nature, it may be used for multiple independent purposes, such as a Hardware Abstraction Layer, a Virtualization Platform, or as a basis for implementing new operating systems. By its simple and abstract design, L4 has a distinguished position among other real-time executives.

The microkernel is the only component that runs in privileged CPU mode. Therefore it is the central point of trust on the platform, responsible for the overall security and stable operation of the system. The microkernel is kept rigorously small, therefore making the system secure and stable.

Since the microkernel has system-wide control, the division of components and resource partitioning are also managed by the microkernel. In this respect Codezero implements the notion of Capabilities to protect and safely multiplex all resources to its run-time components.

Codezero microkernel technical features

General technical features of Codezero are listed below.
General features
  • System partitioning with the concept of containers
  • Fully capability-checked kernel provides:
    • Flexible and configurable resource management
    • Fine-grain security
  • CML2-based kernel and system configuration interface
  • Written in C using a familiar open-source coding style
  • Support for the ARM architecture, including ARMv7, Cortex-A9
  • Multicore enabled
  • Portable design and structured layout
  • Focus on embedded systems
  • Open-source license option and development model
Codezero's system calls provide the following mechanisms on an embedded system:
  • Thread creation, destruction, and management of thread execution
  • Address-space creation, deletion, and manipulation
  • Interprocess communication
  • Creation of virtual-to-physical address mappings
  • Dynamic management of resource access via capabilities
  • Userspace shared-memory synchronization
  • Cache and TLB control
  • System-on-Chip security, power, and error-recovery management
Real-time features
  • The microkernel supports kernel preemption, i.e., even tasks running inside the microkernel may be preempted if their timeslice expires.
  • All blocking operations are interruptible. A task sleeping on an IPC queue, a lock, or any waitqueue may be interrupted.
  • Codezero has a priority-based scheduler. As such, timeslices are distributed based on the priorities.
  • There are very few locks in the microkernel; consequently concurrency conflicts are avoided and kernel preemption is enabled most of the time.
Generally, Codezero has been designed from the start to incorporate the necessary infrastructure for real-time performance.