The ca_prng is a Cellular Automata with 32 cells, implemented as a 32 bit wide register. Each register has separate update logic that looks at the current state of the register and its two nearest neighbours (with wrap around). Cell state update latency is thus one cycle.

The ca_prng core supports user controllable initial state pattern, state update as well as changing the update rule.

The ca_prng core is a positive edge triggered synchronous design. All internal registers are equipped with a synhronous, active low reset.

The ca_prng core is provided as RTL source code written in Verilog 2001 compliant code. The ca_prng delivery also contains a testbench that verifies the functionality. Finally the core contains a functional model written in Python as well as documentation.

The provided testbench has been used to verify the core using the ModelSim as well as the Icarus Verilog simulators.

The ca_prng core has been implemented in FPGA tools from Altera and Xilinx. The following table lists the area and speed achieved for the ca_prng as a stand alone project.

Altera Devices (implemented using Quartus 9.0)
Stratix II
Device: EP2S15
ALUT: 106
Reg: 40
Mem: 0
DSP: 0
fmax: 300 MHz

Cyclone III
Device: EP3C5
LE: 234
Reg: 40
Mem: 0
Mult: 0
fmax: 250 MHz

Xilinx Devices (implemented using ISE 11.0)
Spartan 3A
Device: xc3s50a-5
Slices: 93
Reg: 48 (replicated update_rule_reg)
Mem: 0
Mult: 0
fmax: 250 MHz

Device: xc5vlx30-3
Slices: 42
Reg: 40
Mem: 0
Mult: 0
fmax: 400 MHz