I am building a CAN controller project on an actel Proasic 3 chip using this core, but the developping software Libero cannot recongnize the module "actel_ram_64x8_sync, actel_ram_64x4_sync, actel_ram_64x1_sync" and I cannot find any information about this three module on actel website, either. Is this core can only be applied on certain FPGA of ACTEL, or the three module should be created by myself? What is the exact reason of this problem?
You have to generate your own Makros for these entities using the IP Core Generator inside your Libero Tool. I should be located on the rightern side of your Libero project window.
how to define the macros in case of xilinx.I need to define RAMB4_S8_S8 ,RAMB4_S4_S4 and RAMB4_S1_S1 what should be the value of these macros