Mohor, Igor

CAN Protocol Controller

In using the CAN protocol Controller I would also like to give it proper attribution, but the license wasn't clear to me.

Would it be possible to fix the license pick on the project page, and possibly add licensing headers to the project files?

Best regards // Andreas

CAN protocol controller license

I am getting a crc error when running the simulation manual_frame_basic.
"*E (210234400) ERROR: CRC error (Calculated crc = 0x605b, crc_in = 0x4248)"
Anyone have a solution to this issue?

crc error when running main frame basic

Hi all ,

I don't know how to use the testbench in Modelsim , can anyone help me for that ? Modelsim doesn't want to compile testbench file.

TestBench

You should not try to mimic the AN97076 interface as this makes everything more complex. In an FPGA you have advantages compared to a MCU, you should use them. Having to configure multiple wishbone register to send a single frame is a pain when implemented in a real system.

Do the same for the acceptance filter/maks and it will remove the need for long and error prone sentences things like that:
wire we_tx_data_6               = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status; 

  Here is what I would do.

1) Use a single register that can be directly accesssed from can_top for the whole identifier 36bit or 19bit.  Let the user of the can_top module make is own register and place them using concanetation is easy

2) It will remove odd problems like the need to reverse order the tx_data_4 register. ( using r_tx_data_4[7:3] instead of r_tx_data_4[4:0] fix this problem too )

3) Use standard state machines. The state machine that you have in can_bsp is difficult to follow.

Doing all this will render the code more readable, reduce the number of inputs/ouputs considerably and simplify use.

Simplify code

Please let me know how to use this code with SJA1000. I am in a little time budget and need to use CAN in my project. 

Thanks.

Request for information regarding SJA1000

I am trying to dumb the core on spartan 6 but it has encountered an error 

ERROR:NgdBuild:604 - logical block 'i_can_bsp/i_can_fifo/fifo' with type
   'RAMB4_S8_S8' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'RAMB4_S8_S8' is
   not supported in target 'spartan6'.
similar for RAMB4_S1_S1 and RAMB4_S4_S4
I got the reason for this problem that macros need to be defined but how and where to define them.

Finding difficulty in defining macros

Assuming this module should match the register settings of the SJA1000, the BRP controls are off by a factor of 2.  Modified line 257 of can_btl.v to correct.

just remove the <<1
was assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
fix assign preset_cnt = (baud_r_presc + 1'b1);           // (BRP+1)

Baud Rate Prescaler off by 2x

In my implementation the CAN clock is at 24MHz, and the Wishbone clock is at 75MHz.  Was having problems with registers behaving erratically and noticed a cross clock issue with the wishbone cycles.  The following change fixed it for me.

In can_top.v:
 Line 800 was:
        cs_sync2     <=#Tp cs_sync1            & (~cs_sync_rst2);
 I replaced to become:
        cs_sync2     <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_sync1;

Since wb_cyc_i and wb_stb_i are being sampled with the can clock (clk_i), and they are being generated synchronous to the wb_clk_i, this change makes sure they exist for at least 2 cycles of the can clock.

Cross clock issue with wishbone

For all that are trying to use this core:

Ensure, that you reset the core before testing! I am using Wishbone and ran into problems before I tried to assert the WB_RST wire for some clock cycles before testing. Tested the core in a Spartan 6 FPGA.

Maybe its a good idea to add an automatic reset@startup mechanism.

Cheers,
Simon

Reset

Hello I have problems with the reception Messages in the Basic mode. I am using the core on hardware, on an altera cyclon 3, without wishbone. Transmitting works fine.
It seems to a be a bit shifting. It could be a problem within the fifo. But I can't find the problem. Had anybody the same problem? Any solution?

Thank You in advance!

BR F.

Problem with reception in Basic mode

Hi

in some scenarios where wrong frames are received, the first valid frame received afterwards can have corrupted data.

The problem is in can_bsp.v line 1017..1026

always @ (posedge clk or posedge rst)
begin
  if (rst)
    byte_cnt <= 3'h0;
  else if (write_data_to_tmp_fifo)
    byte_cnt <=#Tp byte_cnt + 1'b1;
  else if (sample_point & go_rx_crc_lim)
    byte_cnt <=#Tp 3'h0;
end

This byte_cnt holds the index where to write a received data to a temporary buffer. The problem is, this is reset to 0 after the data is complete.
In case a frame started correctly and in the middle of the data an error happens, the byte_cnt is not reset and the next frame starts to write the data at the wrong index.
To fix this, the byte_cnt should be reset when the frame is going to receive the data bytes:

always @ (posedge clk or posedge rst)
begin
  if (rst)
    byte_cnt <= 3'h0;
  else if (write_data_to_tmp_fifo)
    byte_cnt <=#Tp byte_cnt + 1'b1;
  else if (go_rx_data)
    byte_cnt <=#Tp 3'h0;
end

cu
Frank

Corrupted data, bug found

The documentation (SJA1000 from Philips Semiconductor) describes a pin to the SJA1000 IC that selects Motorola or Intel mode.  This mode changes several functions in the controller as well as timing for read/write cycles.

I am wondering what mode the Opencores CAN controller uses and if that mode is selectable.  I will update this post with the answer as soon as possible.

Motorola vs. Intel modes

incorrect received messages from fifo after some time

Has anybody ever used the testbench and can explain how to use it?

I see that it contains lots of not-synthesizeable code, so which simulation tool do I have to use?
Does it work with ModelSim?

HOWTO use testbench

How fast is the Wishbone Clock? clk_i for the can controller runs at 24 Mhz. But how many Mhz at the Wishbone clock entry? Also 24 Mhz?

Wishbone Clock

Hey,
I am working atm at a SOPC-Builder Port.
Lil Question: the clk_i entry needs to geht 24Mhz.
How fast should be the wishbone clk? also 24Mhz?

Untitled bug

Please add "Verilog"

to the language field in the description here:

http://www.opencores.org/project,can

Thanks so much.

language

When "read_irq_reg" and "(transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)" is active both at the same time, the register "transmit_irq" do not set and IRQ is lost.
I am sorry, but my English is bad.

The current code:

reg transmit_irq;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    transmit_irq <= 1'b0;
  else if (reset_mode || read_irq_reg)
    transmit_irq <=#Tp 1'b0;
  else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
    transmit_irq <=#Tp 1'b1;
end

should be:

reg transmit_irq;
always @ (posedge clk or posedge rst)
begin
  if (rst)
    transmit_irq <= 1'b0;
  else if (reset_mode)
    transmit_irq <=#Tp 1'b0;
  else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
    transmit_irq <=#Tp 1'b1;
  else if (read_irq_reg)
    transmit_irq <=#Tp 1'b0;
end

can_registers.v: transmit_irq no set

I know very little about Verilog (I do know VHDL) and have run across the following warnings from Altera Quartus II V8.1:


Warning (10236): Verilog HDL Implicit Net warning at can_top.v(589): created implicit net for "rx_inter"


+---------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                           ;
+----------------------------------------------+----------------------------------------+
; Register name                                ; Reason for Removal            ;
+----------------------------------------------+----------------------------------------+

; can_bsp:i_can_bsp|overload_request_cnt[0..1] ; Lost fanout                    ;
; can_bsp:i_can_bsp|overload_frame_blocked     ; Stuck at GND due to stuck port data_in ;

; can_btl:i_can_btl|delay[3]                   ; Stuck at GND due to stuck port data_in ;

; Total Number of Removed Registers = 4        ;                               ;
+----------------------------------------------+----------------------------------------+



The first warning about the implicit net can be "fixed" by adding a wire declaration for the indicated net.  However, the warnings about register removal causes me considerable concern.  If they are declared I assume they are needed so why are the tools removing them?  Has anyone else run into this issue?  Is there a bug in the design or a problem with the Verilog code?


Thanks for your help;

Brent Zajac

register removal

I am building a CAN controller project on an actel Proasic 3 chip using this core, but the developping software Libero cannot recongnize the module "actel_ram_64x8_sync, actel_ram_64x4_sync, actel_ram_64x1_sync" and I cannot find any information about this three module on actel website, either. Is this core can only be applied on certain FPGA of ACTEL, or the three module should be created by myself? What is the exact reason of this problem?

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CAN Protocol Controller