Mohor, Igor

CAN Protocol Controller

Controller Area Network protocol is not available at the site www.logic_xpress.com which is mentioned in this site .

I need it urgently!!!!!!!!!!.

Igor Mohor:
Use Verilog version, VHDL is not up-to-date and is not available any more. Don't send mail requests for it.

Controller area network protocol is not available!!

Sir, even though the full verilog code is available for the controller, it is still difficult to understand the code without any documentation.

the verilog code needs documentation

Hi

In can_registers.v there was a change in rev 1.33 to make the irq reset one cycle after a read of the irq register.

However, my interpretation of the SJA1000 datasheet is that the IRQ should also clear after a write to 'release receive buffer' (bit 2 of command register).
(see note 2 at the top of page 32 of the data sheet referring to the irq register), specifically: "Giving the command ‘release receive buffer’ will clear RI temporarily"

This is useful if you only active the receive interrupt, in which case it is not necessary to check the irq register, and can just write to release the receive buffer.

IRQ reset bug

Hi

Is single-shot transmission (as per SJA1000 documentation)
supported for this core? i.e. you can transmit frame just once
and no retries are attempted if it doesn't succeed?

Great core btw, thnx, will send full report when I have tested
fully in my design
Tom

single shot transmission

hallo,
i have some questions about the registers.
It seems like the Register assignment of the Pelican SJA1000. It was same from Register 1 to Register 7, and from Register 10 to 19 was tx_data_0 to tx_data_9, from Register 20 to Register 29 the Rx_data_0 to Rx_data_9 and Register 31 was clock_divider Register. Was ist right? and what was the use of register 8,9,30? and are there also any other registers? 
thanks for the answers in advance.

Register Assignment

Is the VHDL version tested at all? I tried to compile the code with modelsim and I got allot of syntax errors.


ANSWER:
As far as I know the VHDL code was rewritten in VHDL (and is not up-to-date). I know nothing about testing it. Ask the author of the VHDL part.
And please use the cores@opencores.org mailing list for questions. This section is reserved for "BUG reporting".
Regards,
      Igor Mohor

Is the VHDL version not tested at all?

Although the Verilog source looks to be well structured, it is still very difficult to follow.
The SJA1000 documentation is good to describe the operation of the controller but I feel some additional code specific documentation is needed in order for this CAN Controller to be useful to the designer. 
Even some documentation on the interfacing and synthesis would be helpful.

Research Engineer.

This verilog code is difficult to follow.
It would be very useful if some documentation was given on how to interface to it.
The SJA1000 documentation is good to describe the operation of the IP, but I think some code specific documentation is needed in order for this to be useable. 

Regards,
David.

Research Postgrad.

It would be nice if the Wishbone I/F also supported 32 bits. The other wishbone I/P I am using is 32 bit (PCI/Wishbone bus bridge)

32 bit wide Wishbone I/F

This core needs documentation to tell the designer how to use it.  At the very least, the following things should be documented:

1) A description of each top-level port.  What is the difference between "clk_i" and "wb_clk_i".  Can they be connected to the same clock?  What is their relationship?
2)A register map for the internal registers for the core.
3)A description of each file.  
4)There should also be sample synthesis and simulation scripts.
5)Instructions for how to integrate the core and get it working as part of a bigger design.  How do I know what value to load into the prescaler register?  What other registers do I need to read or write?  How does the interrupt work?  When does it go active?

This is just the tip of the iceberg and all of this is very important.  The core is nearly useless without at least some basic documentation.

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CAN Protocol Controller