CAN Protocol Controller

Is the VHDL version tested at all? I tried to compile the code with modelsim and I got allot of syntax errors.

ANSWER: As far as I know the VHDL code was rewritten in VHDL (and is not up-to-date). I know nothing about testing it. Ask the author of the VHDL part. And please use the cores@opencores.org mailing list for questions. This section is reserved for "BUG reporting". Regards, Igor Mohor

The CAN VHDL core will complie in ModelSim with the following commad line

vcom -93 -explicit *.vhd

The core is not up-to-date according to the Verilog core and has not been tested in hardware.