CAN Protocol Controller

This verilog code is difficult to follow. It would be very useful if some documentation was given on how to interface to it. The SJA1000 documentation is good to describe the operation of the IP, but I think some code specific documentation is needed in order for this to be useable.

Regards, David.

1. For interfacing to the 8051 CPU read the 8051 documentation.
2. For interfacing to the WISHBONE bus read the WISHBONE documentation.
3. For understanding the CAN protocol read the CAN standard (from Bosch).
4. If you believe that additional documentation is needed, feel free to write it. Put inside whatever you believe is good to have or understand. Be usefull to the opencores community.

Regards, Igor M. (The CAN core author)

Hello! It is difficult to follow the VHDL code so is it possible to supply a block detaild block diagram and description for the code. Thanks very much in advance

Verilog version was converted to the VHDL and is at the moment not up-to-date. This was done by Shehryar Shaheen. So if you want to have a working version, take the one written in verilog. Regarding the block diagram: Go through the code and you'll see in 5 minutes that it has the following modules: TOP (connecting all modules + synchronization of the host interface), BSP (bit stream processor is running most of the protocol), BTL(bit time logic is in charge for synchronization issues), REGISTERS, FIFO, ACF (acceptance filter). And that's it. If you want to write a document about it, be my guest.

Regards, Igor