You should not try to mimic the AN97076 interface as this makes everything more complex. In an FPGA you have advantages compared to a MCU, you should use them. Having to configure multiple wishbone register to send a single frame is a pain when implemented in a real system.
Do the same for the acceptance filter/maks and it will remove the need for long and error prone sentences things like that: wire we_tx_data_6 = cs & we & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22)) & transmit_buffer_status;
Here is what I would do.
1) Use a single register that can be directly accesssed from can_top for the whole identifier 36bit or 19bit. Let the user of the can_top module make is own register and place them using concanetation is easy
3) Use standard state machines. The state machine that you have in can_bsp is difficult to follow.
Doing all this will render the code more readable, reduce the number of inputs/ouputs considerably and simplify use.