In my implementation the CAN clock is at 24MHz, and the Wishbone clock is at 75MHz. Was having problems with registers behaving erratically and noticed a cross clock issue with the wishbone cycles. The following change fixed it for me.
In can_top.v: Line 800 was: cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2); I replaced to become: cs_sync2 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_sync1;
Since wb_cyc_i and wb_stb_i are being sampled with the can clock (clk_i), and they are being generated synchronous to the wb_clk_i, this change makes sure they exist for at least 2 cycles of the can clock.
For some reason, code snippets didn't come through... Trying again:
Line 800 should be: "cs_sync2 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_sync1;"
ok, still not working...
Line 800 should include wb_cyc_i & wb_stb_i