Issue List
Reset #31
Open simon.gansen opened this issue over 5 years agoIdea
simon.gansen commented over 5 years ago

For all that are trying to use this core:

Ensure, that you reset the core before testing! I am using Wishbone and ran into problems before I tried to assert the WB_RST wire for some clock cycles before testing. Tested the core in a Spartan 6 FPGA.

Maybe its a good idea to add an automatic reset@startup mechanism.

Cheers, Simon