Please let me know how to use this code with SJA1000. I am in a little time budget and need to use CAN in my project.
Has anyone gotten this core to work. I have connected it to a NEO430 core processor but I am only getting what looks like FFs being transmitted on my Tx line.
I have 8 instances with external transceivers up and running with Xilinx Vivado on a Zynq 7000. Minor tweak was needed for the FIFO as the RAMB4_* functions are now obsolete, used xpm_memory_sdpram(...) instead.
I hooked it up to the CPU with a Wishbone AXI bridge (https://opencores.org/projects/wishboneaxi).
Nice work of Igor and I'm so happy to not have to fork out $15k on Xilinx CAN IP for my hobby project!