OpenCores
Issue List
Untitled bug #24
Open hellsmurf opened this issue almost 10 years ago
hellsmurf commented almost 10 years ago

Hey, I am working atm at a SOPC-Builder Port. Lil Question: the clk_i entry needs to geht 24Mhz. How fast should be the wishbone clk? also 24Mhz?


Assignee
No one
Labels
Request