Datetime

Description

2023/02/28 Added a System Verilog version of the core which uses a 32-bit interface. The new core has a configuration space to it allowing the I/O address and interrupt signal line to be adjusted programmatically. Improved snapshot capability works for either read or write of registers. The core is defaulted to respond to the address range $FEF30000-$FEF3FFFF.

This is a date/time keeping core. It uses an external 100,60 or 50 Hz time-of-day signal to update a group of BCD counters which record the date and time. The date and time is presented as a 16 digit BCD format YYYYMMDDHHMMSSJJ which fits into a 64-bit word.

Features

- optional 50,60, or 100 Hz time-keeping
- 64 bit bus interface
- internally decoded to respond in address range $DC0400-$DC0418
- Mars timekeeping option (millennium style calendar)
- leap year tracking
- independent system bus and time-of-day clocks
- alarm setting