DDR 4 memory controller
Project maintainers
Details
Name: ddr4_controller
Created: Oct 30, 2025
Updated: Oct 30, 2025
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Oct 30, 2025
Updated: Oct 30, 2025
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Memory core
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
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The url of the svn repository is: https://opencores.org/websvn/listing/ddr4_controller/ddr4_controller
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