DDR 4 memory controller
Project maintainers
Details
Name: ddr4_controller
Created: Oct 30, 2025
Updated: Jul 13, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
Created: Oct 30, 2025
Updated: Jul 13, 2026
SVN: No files checked in
Bugs: 0 reported / 0 solved
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Other project properties
Category:Memory core
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
The project is DDR4 memory controller.The intention of the project is design and develop all the features of DDR4 memory controller as well as implement it in FPGA.
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