OpenCores

EtraxFS & Xilinx FPGA dev board with building blocks

Project maintainers

Details

Name: elphel_353
Created: May 17, 2007
Updated: Aug 31, 2018
SVN: Check description below for external links
Bugs: 1 reported / 0 solved
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Other project properties

Category:Prototype board
Language:Other
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

EtraxFS & Xilinx FPGA dev board with building blocks

Elphel 353/363 is an OpenHardware a board using GNU/Linux. It is based on EtraxFS CPU and Spartan 3e FPGA.

Elphel's 353/363 primary usage is network reconfigurable camera. But our hardware can be used to develop very different and flexible solutions.

We have several boards:

* 10353 - processor board (computer part of the camera)
* 10338 - 5MPix sensor board for 353-series cameras
* 10357 - solid-state storage (can accommodate up to 8 CF cards - 128GB total)
* 10359 - multifunction multiplexer/FPGA processing board. Can be used to connect up to 3 of the sensor boards (i.e. 10338, 10347) to one processor board. It can process the image data too.
* 10347 - controller part of a two-board stack (currently with 10342 or 10344) to connect 35mm format CCD image sensors
* 10342 - sensor board (requires 10347) for the Kodak 11MPix KAI-11002 CCD image sensor
* 10344 - sensor board (requires 10347) for the Kodak 16MPix KAI-16000 CCD image sensor

All schematics, layout, FGPA code and GNU/Linux sources are available inside each camera or from our web site. http://www.elphel.com

Features

Features of 10353 (mother board):
* Axis ETRAX FS
* 10/100 Ethernet with 802.3af (Power Over Ethernet)
* High-density 30-pin inter-board connector
* IDE port from the CPU is routed to additional 40-pin high density connector
* Sensor interface uses LVTTL 2.5V signals instead of 3.3V
* FPGA is now Xilinx (R) Spartan3e 1200K gates
* System memory - 64MB (SDRAM)
* System flash memory - 128MB (NAND flash)
* Image memory - 64MB (DDR SDRAM)
* Cypress programmable CY22393 3-PLL clock generator provides clock for the CPU and FPGA, all the frequencies can be adjusted when needed.

Status

* Schematics: done
* PCB Layout: done
* PCB assembly & testing: done
* Linux 2.6: done
* FPGA code: done

For more information please visit our site: http://www.elphel.com & our wiki: http://wiki.elphel.com